Block interleaving and deinterleaving method and device therefor

ABSTRACT

A process for interleaving blocks of P packets each including L binary words, the interleaving being carried out by writing the data to an interleaving memory in a given order and by reading them back in an order corresponding to the interleaving. After having read, at a given address, a data item corresponding to a block b-1, a data item corresponding to the block b is written at the same address.

BACKGROUND

The present invention relates to a process for blockwise interleavingand deinterleaving of data, as well as to a device implementing thisprocess. The invention applies in particular to the interleaving ofdigital data before their transmission and to the deinterleaving afterreception.

It is known from the prior art to associate the techniques of errordetection and correction and interleaving in order to make thetransmission of digital data reliable.

For an error correcting code such as the Reed-Solomon code, the packetof binary words to be transmitted is supplemented with a number of extrawords, making it possible to correct up to a given maximum number oftransmission errors. When this maximum number of errors is exceeded, thecorrecting code is no longer adequate. This may be the case inparticular if a burst of errors corrupts several contiguous words.

In order to increase the effectiveness of the correcting code, severaldata packets are interleaved. This technique consists in transmitting insuccession words arising from different packets. By not transmittingeach packet in one go, it is possible to spread the consequences of aburst of errors over several packets, and thus to remain within thelimits of the correcting code.

The interleaving, at the sending module, is generally carried out bywriting the data to a memory in a certain order, and by reading themback in a different order for transmission. The deinterleaving, at thereceiver, is carried out in the inverse manner, by writing the data tothe deinterleaving memory in accordance with the order for reading theinterleaving memory, and by reading the data back in accordance with theorder for writing to the interleaving memory.

Consider P packets to be interleaved, each comprising L bytes. These Ppackets constitute a block B. An interleaving of depth P is said to becarried out by rearranging the bytes of the P packets in such a way asto separate two successive bytes of a given packet by P-1 bytes arisingfrom the P-1 other packets.

FIG. 1 shows a memory making it possible to carry out this interleaving.In order to simplify the account of the prior art, this memory includesP columns of bytes. The addresses increase from left to right and fromtop to bottom, as FIG. 1 shows.

This memory is written to by writing the first byte of the first packetat the address 0, the second byte at the address P, and so on until thelast byte (byte L-1) at the address (L-1)P. These addresses correspondto the first column of the memory. In the same way, the second packetwill be written at the addresses 1, P+1, . . . (L-1)P+1 of the secondcolumn. We continue thus up to the last packet and the last column. Theorder of writing is illustrated in FIG. 2.

By generalizing, it may be stated that byte 1 (with 1 ε [1,L]) of packetp (with p ε [1,P]) of block b (with b ε [1,B]) will be written at theaddress (b-1)LP+(p-1)+(l-1)P of the memory.

Reading will be performed in the order of the addresses, that is to sayby reading row after row (see FIG. 3). Hence, the first bytes of all thepackets are read initially, followed by the second bytes and so on.Interlacing is therefore achieved.

This write/read scheme implies that it is necessary to write a largepart of the data of a block B before being able to read it.Specifically, E=(L-1) (P-1)+1 bytes will have to have been writtenbefore reading the first byte at the address 0. If this criterion is notcomplied with, reading will occur at some time or another at an addresswhich has not yet been swept by the writing.

FIG. 4 illustrates the progress of the write address and read address inthe case where P is taken equal to 3 and L is taken equal to 7. Time isrepresented as abscissae, whilst the addresses of the interleavingmemory form the ordinates. T represents an elementary clock cycle. Itwill be assumed that for a given cycle, writing is performed beforereading.

SUMMARY OF THE INVENTION

Thereby, when the write address is equal to the read address for thesame cycle T, the corresponding data item is written first before beingread back during the same cycle T.

The sawtooth curve 1 represents the write addresses, whilst thestaircase curve 2 represents the read addresses. The curve 1 makes 6jumps of 3 addresses starting from the address 0, this corresponding tothe writing of the first packet (7 bytes) in the first column. Writingthen resumes at the top of the second column, with the address 1. At thepoint A, that is to say after writing (L-1) (P-1)+1=13 bytes, readingcan begin at the address 0, during the same cycle in which the writingof the thirteenth byte is performed. The read address will beincremented by one unit in each clock cycle. It will be noted that atthe point D the two curves meet. If the reading of the data had beenundertaken earlier than the 13^(th) write cycle, for example in the12^(th) cycle, there would have been an attempt to read at the address 2before a data item had even been written there.

At point B, the writing of the first block of P packets is complete, thelast value having been written at the address (LP-1)=20. The writing ofthe next block then begins at the address LP=21, as illustrated in FIG.2. At the end of the block, the address jump is therefore 1.

The minimum size Delta of the memory is equal to the maximum differencebetween the write address and the read address. In the scheme of FIG. 4,it may be seen that this difference is a maximum at the point C. Thewrite address is LP+(L-1)P. At this moment LP+L bytes have been written.The read address is then LP+L-E=LP+L-(LP-L-P+2)=2L+P-2.

We therefore obtain Delta=LP+(L-1)P-(2L+P-2)+1=2(L-1)(P-1)+1.

Considering the above numerical example, the minimum size of the memorywould have been 25 bytes.

The purpose of the invention is to present an interleaving processmaking it possible to reduce the size of the memories required, whilstsimplifying the addressing of these memories.

The subject of the invention is a process for interleaving blocks of Ppackets each including L binary words, according to which, after havingread at a given address a data item corresponding to a block b-1, a dataitem corresponding to the block b is written at the same address, thesaid process being characterized in that the addresses of theinterleaving memory ranging from 0 to LP-1, the progression of theread/write addresses for a block b is such that:

    a.sub.b (n)=(a.sub.b (n-1)+(L.sup.(b-x)))mod(LP-1) for nε(0,LP-1), n integer,

with

    a.sub.b (0)=1

    a.sub.b (LF-1)=LP-1

and

    bε[1,∞[, b integer

    x≦b, x integer.

The subject of the invention is also a process for interleaving blocksof P packets each including L binary words, according to which, afterhaving read at a given address a data item corresponding to a block b-1,a data item corresponding to the block b is written at the same address,the said process being characterized in that if a_(b) (n) is the stringof read/write addresses in the interleaving memory whose addresses rangefrom 0 to LP-1, the relation between the string of addresses of block band the string of addresses of block b+1 is:

    a.sub.b+1 (n)=LX(a.sub.b (n)) modulo (LP-1) if n≠LP-1,

    a.sub.b+1 (LP-1)=LP-1.

Thus, the memory is filled up by writing the next block in tandem withthe reading of the previous block. Owing to the equality, at any moment,of the read and write addresses, the addressing of the interleavingmemory is greatly simplified. The size of the memory required is thenonly PL binary words.

In the first case, the progression of the addresses for a block b doesnot require a knowledge of the addresses relating to block b-1. Itsuffices to know L, P, b and x.

In the second case, the relation gives the information required to gofrom the addresses corresponding to a block b to those corresponding tothe block b+1. It suffices to know the addresses corresponding to blockb, and the values of L and P.

Obviously, it is possible to go from a block b to a block b+m byapplying this relation m times.

According to a particular embodiment of the invention, there is noreading of data during the writing of the data of the first block. Thedata which could be read at this moment do not normally have anymeaning.

According to a particular embodiment of the invention, there is readingof data during the writing of the first block, and the results of thisreading are not used. There is then no exception as regards theprocessing of the first block.

The subject of the invention is also a device for generating addressesfor interleaving and/or deinterleaving blocks of P packets, each packetincluding L binary words, characterized in that it comprises means ofgenerating, for a block of order b, a constant L.sup.(b-x) modulo (LP-1)with b an integer and x a constant integer less than or equal to b, andmeans of adding a multiple times m (an integer varying from 0 to LP-1)of the said constant to a base address, each resulting value being takenmodulo (LP-1) if the said value is different from (LP-1) or strictlygreater than (LP-1), the result of this addition constituting the readaddress for block b and the write address for block b+1.

According to a particular embodiment, the device for generatingaddresses is characterized in that it receives a clock pulse at thefrequency of the bytes to be interleaved, the device including a clockdivider by P receiving the clock pulse CO, a clock divider by L,receiving as input the output from the divider by P, two adders modulo(LP-1), the second adder performing the modulo calculation only if theresult of its addition is either different from or strictly greater than(LP-1), as well as a buffer register, the first adder possessing a clockinput receiving the output signal from the divider by P, the two inputsof this first adder respectively receiving the output from the sameadder and the output from the buffer register, the adder finallypossessing a reset input, controlled by the signal from the divider by Lor an initialization signal, the output of the first adder beingmoreover connected to the input of the said buffer register, the latteralso possessing a SET input, connected to the initialization signal andenabling it to be set to the value 1, as well as a clock input connectedto the signal from the divider by L, the output of the buffer registerbeing connected to one input of each of the two adders, the second adderreceiving on its other input its own output, which also constitutes theoutput of the device and provides the read/write addresses, the clockinput of the second adder being connected to the signal CO, the resetinput of the second adder being connected to a logic OR with two inputs,which receives the output from the divider by L and the initializationsignal

BRIEF DESCRIPTION OF THE DRAWINGS

Other advantages and characteristics of the invention will emergethrough the description of a particular embodiment of the invention,illustrated by the attached figures, in which:

FIG. 1, already described, represents the addressing scheme of aninterleaving memory,

FIG. 2, already described, represents a known scheme for writing data tothe said memory,

FIG. 3, already described, represents a scheme for known reading of datafrom the said memory,

FIG. 4, already described, represents a simultaneous diagram of progressof the read and write addresses,

FIG. 5 represents a diagram of progress of the write and read addressesin another interleaving memory, the said progress being in accord withan example of implementation of the inventive method,

FIG. 6 represents an embodiment example of a device for implementing theinvention,

FIGS. 7 and 8 represent other embodiment examples of devicesimplementing the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

According to the present embodiment of the invention, it is sought tocarry out the interleaving, of depth P, of groups of P packets of Lbytes in blocks B of PL bytes each. In accordance with the invention, aninterleaving memory of PL bytes will be used. To simplify theexplanations, this memory [lacuna] organized as a matrix of P columns ofL bytes, the memory spaces being addressed from 0 to PL-1 by sweepingthe memory row by row, from top left to bottom right.

FIG. 5 gives the progress of the write and read addresses in accordancewith the present embodiment example. P and L are taken equal to 3 and 7respectively. The memory therefore includes 21 slots, with addresses 0to 20, given as ordinate. The time appears as abscissa.

The first step to be undertaken consists in writing the first block(block b=1). No reading is performed for this first block. To take asimple example of the progression of the write addresses of this firstblock, an incrementation by one address with each data write is chosen,starting from the address 0.

The diagram of the progress of the write addresses of the first block isgiven in the first column of FIG. 5.

The second step consists in reading the data written during the writeperiod for the previous block, in an order corresponding to theinterleaving. The read addresses are calculated from the write addressesof the first block. In the present example, the addresses coincide withthe order of writing. If the P packets are written consecutively to thememory, the bytes will have to be read every L addresses, starting fromthe address 0 (the first bytes of the P packets are read initially, andthen the second bytes etc.). The function giving the addresses in thiscase is:

f(X)=LX modulo (LP-1) when LX≠LP-1

f(X)=LP-1 when LX=LP-1

with X varying from 0 to LP-1.

It will be noted that, when LX is equal to LP-1, the value LP-1 is usedrather than the value 0.

In accordance with the invention, when the data of the first block areread, the data corresponding to the second block are written at the readaddresses. This writing is performed in the same order as before, thatis to say the writing is done packet by packet, starting from the firstbyte of the first packet. The read/write addresses are obviously chosenso as to carry out the interleaving, and are calculated using thefunction f.

The read addresses of the second block are defined by applying f²instead of f, and so on for the succeeding blocks. The following tableof read/write addresses is thus obtained:

    __________________________________________________________________________    0 1 2 3 4 5 6 7 8 9 10                                                                              11                                                                              12                                                                              13                                                                              14                                                                              15                                                                              16                                                                              17                                                                              18                                                                              19                                                                              20                                    0 7 14                                                                              1 8 15                                                                              2 9 16                                                                              3 10                                                                              17                                                                              4 11                                                                              18                                                                              5 12                                                                              19                                                                              6    13                                                                       20                                        0 9 18                                                                              7 16                                                                              5 14                                                                              3 12                                                                              1 10                                                                              19                                                                              8 17                                                                              6 15                                                                              4 13                                                                              2    11                                                                       20                                        0 3 6 9 12                                                                              15                                                                              18                                                                              1 4 7 10                                                                              13                                                                              16                                                                              19                                                                              2 5 8 11                                                                              14   17                                                                       20                                        0 1 2 3 4 5 6 7 8 9 10                                                                              11                                                                              12                                                                              13                                                                              14                                                                              15                                                                              16                                                                              17                                                                              18   19                                                                       20                                        __________________________________________________________________________

The first row corresponds to the write addresses of the first block, thesecond to the read addresses of the first block and to the writeaddresses of the second block, and so on. Transferring from one row tothe next row in the same column is done by applying the function f.

It will be noted that the first and fifth rows are identical, in thecontext of the numerical example used. This periodicity can be used tofacilitate the calculations of the addresses, or their storage in readonly memory.

FIG. 5 gives the graphical equivalent of the above table.

It should be noted that the deinterleaving can be carried out byapplying either the inventive process, or any other deinterleavingprocess, the flow of interleaved data sent by the inventive interleavingdevice being indistinguishable from the flow created by anotherinterleaving device.

According to a variant of this embodiment, and for the purpose ofsimplifying the circuits, reading in the manner described is performedalso during the writing of the first block. The results of this firstread will merely not be taken into account.

FIG. 6 represents diagrammatically an embodiment example of an addresssequencer circuit implementing the invention. The basis of this circuitis the characteristic according to which, for a given block, thetransfer from one address to the next is carried out by addition of aconstant, the result being taken modulo the size of the memory minus 1in the case in which this result exceeds the maximum address of thememory. For example, for the first row of the above table, the constantis 1, for the second row it is 7 (7 being less than or equal to 20, themaximum address), for the third it is 9 (7² modulo 20), for the fourthit is 3 (7³ modulo 20). For the last row we return to a constant 1 (7 tothe power 4 modulo 20). The powers correspond to the powers of thefunction f.

The circuit of FIG. 6 includes an input 1 receiving a clock signal (CO)at the frequency of the bytes to be interleaved, a clock divider by P(2) receiving the clock pulse CO, as well as a clock divider by L (3),receiving as input the output from the divider by P (2).

Three clocks are therefore available, giving one pulse respectivelyevery byte, every P bytes and every block (of PL bytes).

The sequencer circuit moreover includes two adders modulo (LP-1) 4 and5, as well as a buffer register (or "latch") 6. The role of the firstadder 4 is to calculate the constant mentioned above, the latterchanging every PL bytes. The latch 6 stores this value, which is used bythe second adder 5 to calculate the read-/write addresses proper.

The adder 4 possesses a clock input receiving the output signal from thedivider by P 2. The two inputs of this adder respectively receive theoutput from the same adder 4 and the output from the buffer register 6.The adder 4 finally possesses an initialization input RESET, whichallows resetting and which is controlled by the signal from the dividerby L 3 or by the initialization signal INIT.

The output of the adder 4 is connected to the input of the bufferregister 6. The latter also possesses a SET input, connected to aninitialization signal INIT and enabling it to be set to the value 1, aswell as a clock input, connected to the signal from the divider by L 3.The output of the buffer register 6 is connected to one input of each ofthe adders 4 and 6.

The adder 5 receives on its other input its own output, which alsoconstitutes the output of the sequencer circuit and provides theread/write addresses. Its clock input is connected to the signal CO. TheRESET input of the adder is connected to a logic OR 7 with two inputs,which receive the output from the divider by L 3 and to theinitialization signal INIT.

The operation of the sequencer circuit is as follows: an INIT pulse issent to the inputs mentioned above. The outputs of the two adders arethen at zero, whilst the output of the buffer register is at 1. Theoutput of the circuit therefore indicates the address 0.

For one cycle of the clock CO, the reading of the data item of theprevious block is firstly carried out at the address indicated by theoutput of the circuit, and then the writing of the data item of thepresent block is carried out at this same address of the memory. Careshould be taken that the address at the output of the sequencer circuitremains steady during the read/write cycles, since the result of theaddition constituting the address of the next byte should only appearonce these cycles have terminated. A buffer register (not illustrated)receiving the output from the sequencer circuit and controlled by aclock derived from CO will for example be used.

The first pulse on C), announcing via its rising edge the steadiness ofthe first byte to be written on the data bus of the interleaving memory,operates the adder 5 which adds up the values present at its inputs. Inthe present case, a 1 appears at the output, after the rising edge ofthe first pulse on CO. Likewise with each of the succeeding pulses onCO. The adder 5 is therefore incremented from 0 up to LP-1, after whichvalue it is reset by the divider by L 3. The addresses thereforeprogress in the manner indicated in FIG. 5 for block 1.

Meanwhile, the adder 4 counts one pulse of CO every P pulses, its inputconnected to the register 6 being equal to 1. After LP pulses on CO, theoutput from the adder exhibits the value L, stored by the bufferregister 6 which is operated by the pulse from the divider by L 3 atthis time. Care should be taken that the value L at the output of theadder 4 is steady before transferral to the buffer register 6.

For the writing of the second block (and the reading of the first), theprogression of the addresses will occur from L into L memory locations,as indicated by the value stored by the buffer register 6. It is herethat the modulo function of the adder 5 comes into play, so that theaddresses never exceed the maximum address of the memory.

Meanwhile, the adder 4, previously reset, adds L, doing so L times,obtaining L² modulo LP-1. The modulo is taken after each addition, thusreducing the size of the accumulator register of the adder. Finally, thevalue L² mod LP-1 is stored in the buffer register 6.

The operation is then identical for all the succeeding blocks.

According to the example taken, the buffer register 6 is initializedto 1. It is of course possible, according to other embodiments, toinitialize it to another of the values L² mod LP-1, L³ mod LP-1 or L tothe power 4 mod LP-1.

The modulo calculation part of the adders 5 is such that the modulocomes into play only when the result of the addition is strictly greaterthan LP-1. In fact, given the conventions adopted for addressing theinterleaving memory, the address LP-1 would never be obtained if thisprecaution were not taken.

This is equivalent to saying that the modulo is brought into play onlywhen the result is different from LP-1, given that for values which arestrictly less, the modulo does not change the result of the addition.

A comparator of known type will for example be used to compare theresult of the addition with LP-1. In the case in which the comparisonshows that the result of the addition is equal to LP-1, or according toa variant, that it is less than or equal, this result is used directly,without its modulo being taken. The embodying of such a circuit iswithin the scope of these skilled in the art.

Thus, an address generating device and a clock pulse CO at the frequencyof the bytes are available. According to an example embodiment, notillustrated, a clock pulse at the frequency 2×CO is available as is afrequency divider by two creating the clock pulse CO, this double clockpulse being used firstly to read the data item at the address indicatedby the generator device, and then to write the data item of the nextblock at this same address. The circuits for interfacing with the memoryas well as the data buses are easily adaptable by those skilled in theart.

Although in the present particular embodiment, the data are representedin the form of bytes, other formats are obviously possible. Moreover,the particular embodiment above carries out interleaving consisting inchoosing one byte in turn from each packet. The invention is easilyadaptable to other forms of interleaving.

FIG. 7 illustrates another embodiment example of a device implementingthe invention. According to this example, the device includes amicroprocessor 11, a read only memory 12 and the interleaving memory 10.The read only memory includes an integer period of possible addresssequences for addressing the memory. These are for example the addressescorresponding to the first four rows of the table given above. Themicroprocessor 11 addresses the memory 12. For the reading and writingof each block, the memory 12 provides the necessary address to theaddress bus of the interleaving memory 10. The references 13 and 14indicate respectively the data bus entering and leaving the memory 10.

As may be seen, the device is very simple. The addresses are pre-storedin a read only memory. The advantage of this device is among otherthings the fact that few means of calculation are required foraddressing.

According to a variant embodiment of this device, the microprocessor 11is replaced by a simple counter.

FIG. 8 illustrates another embodiment example of a device in accordancewith the invention. The device still includes the interleaving memory10. It also includes a memory 15, as well as a means of calculation suchas a microprocessor 16. The memory contains the constants making itpossible, for the writing of a given block, to go from one address tothe next address. Again taking the example of L=7, P=3, these constantsare, as mentioned earlier: 1, 7, 9 and 3. The microprocessor 16 readsthese constants cyclically as required. It performs the necessaryadditions and the associated modulo calculation. It then addresses thememory 10.

I claim:
 1. Process for interleaving blocks of P packets each includingL binary words, according to which, after having read at a given addressa data item corresponding to a block b-1, a data item corresponding tothe block b is written at the same address, wherein the addresses of theinterleaving memory range from 0 to LP-1 and the progression of theread/write addresses for a block b is such that:

    a.sub.b (n)=(a.sub.b (n-1)+(L.sup.(b-x)))mod(LP-1) for nε(0,LP-1), n integer,

with a_(b)( 0)=0

    a.sub.b (LP-1)=LP-1

and bε(1∞), b integer

    x≦b, x integer.


2. 2. Process according to claim 1, wherein the string of constantsL.sup.(b-x) is stored beforehand.
 3. Process for interleaving blocks ofP packets each including L binary words, according to which, afterhaving read at a given address a data item corresponding to a block b-1,a data item corresponding to the block b is written at the same address,wherein if a_(b) (n) is the string of read/write addresses in theinterleaving memory whose addresses range from 0 to LP-1, the relationbetween the string of addresses of block b and the string of addressesof block b+1 is:

    a.sub.b+1 (n)=Lx(a.sub.b (n)) modulo (LP-1) if n≠LP-1,

    a.sub.b+1 (LP-1)=LP-1.


4. Process according to claim 1, wherein there is no reading of dataduring the writing of the data of the first block.
 5. Process accordingto claim 1, wherein the string of write addresses of the first block is0; . . . ; LP-1.
 6. Device for generating addresses for interleavingand/or deinterleaving blocks of P packets, each packet including Lbinary words, comprising means for generating, for a block of order b, aconstant L.sup.(b-x) modulo (LP-1) with b an integer and x a constantinteger less than or equal to b, and means for adding a multiple times m(an integer varying from 0 to LP-1) of said constant to a base address,each resulting value being taken modulo (LP-1) if said value is isgreater than (LP-1), the result of this addition comprises the readaddress for block b and the write address for block b+1.
 7. Device forgenerating addresses according to claim 6, wherein the device receives aclock pulse at the frequency of the bytes to be interleaved, the deviceincludes a clock divider by P(2) receiving the clock pulse, a clockdivider by L(3), receiving as an input the output from the divider byP(2), two adders modulo (LP-1), one of the adders performing the modulocalculation if the result of its addition is is greater than (LP-1), aswell as a buffer register, the first adder possessing a clock inputreceiving an output signal from the divider by P(2), two inputs of thisfirst adder respectively receiving an output from the same adder and anoutput from a buffer register, the first adder possessing a reset inputcontrolled by a signal from the divider by L(3) or an initializationsignal, the output of the first adder being coupled to the input of saidbuffer register (6), the latter also possessing a SET input, connectedto the initialization signal, and enabling it to be set to apredetermined value, as well as a clock input connected to the signalfrom the divider by L(3), the output of the buffer register beingconnected to one input of each of the two adders, the second adderreceiving at another input its own output, which further comprises theoutput of the device and provides read/write addresses, the clock inputof the second adder being connected to the signal, the reset input ofthe second adder being connected to a logic OR with two inputs, whichreceive the output from the divider by L(3) and the initializationsignal.